1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a structure of a partially-depleted high-voltage MOS (Metal Oxide Semiconductor) transistor using an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
With the development of the technologies of computers and portable devices, the number of ICs (Integrated Circuits) capable of receiving multiple voltages for integrating various functions has been increasing. As a result of the increase of such ICs, technologies integrating MOS transistors ranging from low-voltage to high-voltage MOS transistors into a single chip have been becoming more and more important. Likewise, technologies for reducing power consumption are also required.
To that end, there are some semiconductor devices having an SOI substrate in which elements are formed in a manner such that the elements are isolated and separated from each other. The SOI substrates have some advantages such as latch-up-free operation and electric energy saving.
Japanese Patent Application Publication Nos. 2002-134752 (Patent Document 1) and 2001-119031 (Patent Document 2) disclose techniques manufacturing high-voltage transistors for several tens of volts using the SOI substrate.
In the semiconductor device of Patent Document 1, the impurity concentration of the channel region in contact with the buried oxide film of the SOI substrate is increased compared with the prior art. By doing this, when a predetermined bias voltage is applied to the supporting substrate, the extension of the inversion layer and the depletion layer generated on the boundary surface between the buried oxide film and the channel region can be controlled. As a result, leakage current flowing on the boundary surface between the buried oxide film and the channel region can be prevented.
In the semiconductor device according to Patent Document 2, a similar effect can be obtained by providing a region under the source region, the region having the same conductivity type as that of the channel region and having higher impurity concentration than that of the channel region.
Further, in the semiconductor device of Patent Document 1, to prevent the increase of the threshold value voltage of the MOS transistor, by adding the channel doping process to adjust the impurity concentration of the channel region, it becomes possible to adequately set the threshold value voltage. In Patent Document 2, it is described that no such process is required.
Each of the structures of the semiconductor devices of Patent Documents 1 and 2 enables increasing the threshold voltage of the parasitic transistor formed of the buried oxide film, and therefore is effective for a high-voltage operation.
Further, in the semiconductor device of Patent Document 1, the channel concentration is increased by diffusion. As a result, the threshold value of the primary MOS transistor is increased. To address the increase, the implantation process is added to decrease the channel concentration of the surface side.
Further, in Patent Document 2, it is described that the leakage current is controlled by increasing the concentration of the diffusion layer having the same conductivity type as that of the channel diffusion layer under the source region so as to prevent the current flowing to the source even when the parasitic transistor is operated.
However, regarding the structures of semiconductor devices of Patent Documents 1 and 2, there is no discussion (description) about the concentration ratio between the drain diffusion and the channel diffusion in either of Patent Documents 1 and 2. As a result, a certain level of thickness of the silicon layer is still required; and therefore, the semiconductor devices still have the structure where the source regions are not in contact with the buried oxide film.
Recently, due to concern about the environment, there is a demand for reducing the energy consumption of the semiconductor devices. Further, in analog circuits, there is a demand for reducing the consumption current and increasing the response speed at the same time.
Generally, the MOS transistor operates using a small constant current source. Because of this feature, to increase the operating speed of the MOS transistor, it is necessary to reduce the input capacitance and the output capacitance of the MOS transistor. For example, there are some ICs, such as those used for watches, that have achieved low energy consumption and high-speed circuits by greatly reducing the junction capacitance using the thin-film SOI substrate.
However, there may be no technique available allowing manufacture of high-voltage MOS transistors operating at or more than 60 volts such as in-vehicle ICs and the like based on an SOI substrate having a thin silicon layer in which the source region and the drain region are in contact with the buried oxide film.